Semiconductor wafers must be accurately positioned within fabrication tools at various steps of a fabrication process to properly generate printed features. Accordingly, metrology tools may be utilized throughout a fabrication process to monitor alignment of the wafer within a fabrication tool and/or overlay of printed layers on the wafer. For example, a metrology tool may measure the alignment of a wafer in a lithography tool prior to an exposure step to ensure that a pattern to be exposed is properly aligned with existing features on the sample. By way of another example, a metrology tool may measure the overlay of two or more printed layers on the wafer to characterize the precision of the fabrication process. Alignment data may thus include, but is not limited to, sample alignment data associated with the alignment of the sample in a fabrication tool or overlay data associated with the alignment of two or more printed layers of the wafer.
Metrology tools may typically measure alignment at multiple locations across a wafer and generate a mathematical model to estimate alignment across at least a portion of the wafer. However, the number of alignment measurements performed in a production environment must be selected to balance the accuracy of model with the impact on throughput. Therefore, it would be desirable to provide a system and method for curing defects such as those identified above.